1. Technical Field
This invention relates to interfaces, specifically to the additional hardware required to add a synchronous message broadcast cycle to a VME bus.
2. Description of the Prior Art
The VME bus is a widely accepted standardized bus for connecting a myriad of electronic products together. These products include processor cards, memory cards, and I/O cards. VME bus exchanges occur between a VME bus master and a VME bus slave. A bus member may at one time be able to function as a bus master and at another time function as a bus slave. There may be several bus masters and several bus slaves on a single VME bus.
However the VME bus architects did not provide a message broadcasting facility for the VME bus. The absence of this feature makes the controlling of an array of processes inefficient and precludes accurate synchronization of processes on different VME bus members.
A description of the VME bus is as follows. When a master bus member wishes to communicate to a bus slave, it first arbitrates for bus ownership. Once ownership of the bus is secured, the master places the slaves address on the address bus (which can be 16, 24 or 32 bits wide) and places the operation type on the address modifier bus. The master then asserts address strobe (AS), and places the data on the data bus which can be 8, 16 or 32 bits wide. The master proceeds to assert data strobe (DS), however, the bus cycle is not complete until the slave responds with a data acknowledgement signal (DTACK). This interlocking of the master's data strobe and the slave's DTACK classifies the VME bus as an asynchronous bus.
The VME address modifier bus (AM) is six bits wide and is driven by VME bus masters to tell the targeted slave the size of the address bus and the type of cycle. A VME slave is selected by the decode of the address bus and AM bus (i.e. even if a VME slave's address range is placed on the address bus it will not participate in the cycle if it does not support the accompanying AM code. The VME AM bus has several reserved codes and sixteen user defined codes. Using a user defined AM code to identify the message broadcast cycle ensures that existing VME slaves without the broadcast function will not participate.
Because the VME bus is an asynchronous bus, (interlocking tags, DS from master and DTACK from slave) a problem arises when communicating with multiple slaves, as to which slave returns DTACK indicating that the transfer is complete. Because DTACK is a single signal the master can not distinguish which or how many slaves are answering.
A device produced by Force Computers Inc. is believed to offer a single byte message broadcast addition to the VME bus. Multiple byte messages can be broadcast one byte at a time. This device's receiving hardware generates an interrupt to the local central processing unit (CPU) after each byte indicating that a message has been received. (The local CPU can examine the received message in an internal register). The hardware has two channels for receiving messages. The first channel has an eight byte queue for message storage. The second channel has a single byte register for message storage.
This device's message broadcast is limited to a single byte. Quite often in an array context a single byte is insufficient to control the array elements. Alternatively this device can also send messages in the conventional manner, individually addressing one slave at a time and transmiting a multi-byte message. The master can repeat this until all the slaves in the array have received the message. This method requires that the master re-arbitrate for the bus before sending the message to each slave, and since the time to transmit information is directly proportional to the number of elements (bus slaves) in the array, this time delay limits overall performance. Also, sending control information across the VME bus to one bus slave at a time in a sequential fashion precludes synchronization of the processes because the control information arrives at each bus slave at differing times. In addition, due to the asynchronous interlocking cycles the standard VME bus cycle is limited in speed because of the round trip time of the handshaking signals (data strobe and DTACK).
In order to control an array of processes and provide an accurate means of synchronization between tasks it is desirable for a bus master to communicate with more than one slave at a time. In the prior art devices, after asserting data strobe the bus master must wait for the bus slave to respond. If the bus master were to address multiple slaves at one time, the master would have to wait for all the addressed bus slaves to respond by nature of the interlock between data strobe and DTACK. Because the VME bus has only one DTACK signal it is not possible for the master to determine if all the addressed slaves are responding ready. In addition asynchronous communication with bus interlocks is inherently slow due to round trip propagation time of the interlocking tags.
Accordingly, various objects of this invention are to:
1) add a synchronous message broadcasting cycle to a VME bus; PA1 2) provide a means for event synchronization; PA1 3) provide the necessary hardware to allow for synchronous message broadcasting; and PA1 4) introduce a message broadcasting cycle to the VME bus so as to promote downward compatibility.